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From you post, if i use the ADC as an Avalon-ST source in SOPC builder, can i connect it to a SGDMA core directly? since SGDMA has its own FIFO? Ultimately, I want to fill ADC data to the SRAM with SGDMA as fast as possible(hopefully at ADC sampling speed).
Could the SGDMA read ADC data, store in its FIFO, and write to its connected SRAM simultaneously? i mean, is it dual clock capable?
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If the SGDMA controller is not sufficient, then write your own component using dual-ported RAM or a dual-clock FIFO.
Before attempting to implement anything in hardware, you should simulate your design to see how well clock-domain crossing is implemented.
Cheers,
Dave
Honored Contributor
