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I was also using an SOPC clock that was the same frequency as the ADC. If your ADC is running at a different frequency, and with a different width, then you could add a dual-clock FIFO to this component, and then you would implement the ready/valid controls based on FIFO status bits.
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First of all, thank you very much on the example file you sent me, it is very helpful.
From you post, if i use the ADC as an Avalon-ST source in SOPC builder, can i connect it to a SGDMA core directly? since SGDMA has its own FIFO? Ultimately, I want to fill ADC data to the SRAM with SGDMA as fast as possible(hopefully at ADC sampling speed).
Could the SGDMA read ADC data, store in its FIFO, and write to its connected SRAM simultaneously? i mean, is it dual clock capable?
Thanks,
Michael
Honored Contributor
