To build a FIFO using SRAM

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From your previous post, you said i need to design the input port for Avalon ST? I don't quite know how to start.

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The ADC has no support for back-pressure, and it has valid data on every clock, so an Avalon-ST source component is basically;

aso_data <= adc_data;

aso_valid <= '1';

If you have to use control registers to setup the ADC, then that would involve an Avalon-MM slave registers interface.

The next step is to use SOPC Builder or Qsys to create the _hw.tcl file to recognize this component as an SOPC component. Use the templates provided within that tool.

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Can i use PIO core to supply the stream or a DCFIFO(input from ADC and output to ST sink of SGDMA) ?

If i transfer from DCFIFO to SRAM, can i use memory-to-memory configuration of SGDMA?

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You cannot use the PIO component. You need your own custom Avalon-ST component as described above. You should be able to use the SGDMA controller to connect the Avalon-ST port of the ADC to the Avalon-MM interface on the SRAM.

Alternatively, you can create an Avalon-MM master for the ADC interface, and use that to write to the SRAM. But in that case, you would need to include rate-matching FIFOs. The SGDMA controller should have that already (or the fabric that gets created will have it).

Cheers,

Dave