To build a FIFO using SRAM

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So, basically.. this is just to create an input port for ADC data to enter to the SGDMA core in the SOPC built block?

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The block is to get the ADC into SOPC Builder as an Avalon-ST source. From there you can make a connection to an Avalon-ST sink.

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Why is the valid bit asserted all the time? it does not go invalid? then whats the point of having a valid bit?

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Avalon-ST interfaces normally have ready, valid, and data signals. Its generally just easier to include them all. Whether you implement them, depends on what you are trying to do. For a quick-and-dirty test, not implementing them is fine.

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Since you said the process is quite easy, do you think you can make this component in SOPC and send it to me? i really need to look at examples to learn to do it right, so many things can go wrong the first time. This is very new to me.

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Here's an example from the Stratix II DSP kit. I was connecting this ADC to an Avalon-ST sink that would accept data on every clock, so I did not need to implement backpressure. I was also using an SOPC clock that was the same frequency as the ADC. If your ADC is running at a different frequency, and with a different width, then you could add a dual-clock FIFO to this component, and then you would implement the ready/valid controls based on FIFO status bits.

Note: the _hw.tcl file uses a relative path to the .vhd source, since I keep the _hw.tcl files in a scripts/ folder, and the VHDL in a src/ folder for each project.

Cheers,

Dave