Honored ContributorWhy does the same clock path have different IC delays calculated for the launch and the latch clock? Is the STA using different operating conditions or delays? - for example max for launch and min for latch?
ex launch -0.278 ; 1.757 ; RR ; IC ; 1 ; LABCELL_X64_Y46_N20 ; reset_and_clocks|clk_200|datac latch: 4.471 ; 1.697 ; RR ; IC ; 1 ; LABCELL_X64_Y46_N20 ; reset_and_clocks|clk_200|datac
Honored ContributorGood eye. This is On-Die Variation, and is variation within a given operating condition, not across different ones. Common Clock Path Pessimism should remove most of that variation on the clock tree. I discuss these in Section 5 of the following:
http://www.alterawiki.com/wiki/timequest_user_guideHonored ContributorYes clock pessimism did add back .28ns in the latch path
However for my timing violation it looks like a clock buffer CLKCTRL_G4 was added on the launch path with a total delay of ~2.2 ns that is not in latch path 2.155 ; 2.052 ; RR ; IC ; 1 ; CLKCTRL_G4 clk_sys~clkctrl|inclk ; ; 2.332 ; 0.177 ; RR ; CELL ; 15279 ; CLKCTRL_G4 ; clk_sys~clkctrl|outclk How can I fix that? Can I force a buffer in the launch path?Honored ContributorIs there something in your design that would make it do that? It should be going through two global buffers without a reason. That being said, I think I saw it once and filed it with Altera. I think the way I got around it was assigning the signal to a Global clock in the Assignment Editor. It already was doing that, but tricked it not to do it again. Don't ask me why...
Honored ContributorThe clock is gated and also has clock mux to select between two clocks so maybe that causes the buffer insertion. But why in only the launch path?
Since I am new to FPGAs how do I know if it is a Global clock and how to assign it if it isnt? Should I create a generated clock on the output of the mux and assign it to a Global clock?Honored ContributorI am now trying the Altera Clock Mux Megafunction to see if I get better results
ALTCLKCTRa ALTCLKCTRa (Honored ContributorGated clocks are the bane of FPGA design. Unlike an ASIC(if that's your background), the fitter can't add/remove delays to the clock tree to balance them out. What you're doing is a good solution. Converting to clock enables when possible is another solution. In general, try to avoid them, and if you can't try to minimize interfaces between gated and non-gated domains.
Honored ContributorNo go - I get error - the ALTCLKCTL does not accept the XAUI interface rx_clk as a source
Error: inclk[0] port of Clock Select Block "ALTCLKCTRa:ALTCLKCTRa|ALTCLKCTRa_altclkctrl_lef:ALTCLKCTRa_altclkctrl_lef_component|sd2" is driven by an illegal source, but must be driven by a clock pin or a PLL's CLK or FBOUT output File: /home/llocascio/ETH10G_PP/ALTCLKCTRa.v Line: 67 Info: Input port INCLK[0] of node "ALTCLKCTRa:ALTCLKCTRa|ALTCLKCTRa_altclkctrl_lef:ALTCLKCTRa_altclkctrl_lef_component|sd2" is driven by XAUI_PHY:XAUI_PHY|altera_xcvr_xaui:xaui_phy_inst WHat is the FBOUT option?Honored ContributorFBOUT is PLL feedback clock output
I am tryingto set a global signal to my clk_sys and get error set_global_assignment -name GLOBAL_SIGNAL clk_sys ERROR: Assignment is not a global assignment: GLOBAL_SIGNAL -- it is an instance assignment. Specify a global assignment name or use the instance assignment commands. I also tried set_global_assignment -name GLOBAL_SIGNAL -entity clk_sys ERROR: Missing <value> for "GLOBAL_SIGNAL" assignment. Specify the required value. This is RTL assign clk_sys = USER_DIPSW1? clk_200_pll : tx_clk_clk ; What is correct syntax to set a global signal on clk_sys?
