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Honored Contributor
Honored ContributorSTA Timimg Report Question
Why does the same clock path have different IC delays calculated for the launch and the latch clock? Is the STA using different operating conditions or delays? - for example max for launch and min fo...
Altera_ForumHonored Contributor
Honored ContributorYes clock pessimism did add back .28ns in the latch path
However for my timing violation it looks like a clock buffer CLKCTRL_G4 was added on the launch path with a total delay of ~2.2 ns that is not in latch path 2.155 ; 2.052 ; RR ; IC ; 1 ; CLKCTRL_G4 clk_sys~clkctrl|inclk ; ; 2.332 ; 0.177 ; RR ; CELL ; 15279 ; CLKCTRL_G4 ; clk_sys~clkctrl|outclk How can I fix that? Can I force a buffer in the launch path?
