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Altera_Forum
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14 years ago

STA Timimg Report Question

Why does the same clock path have different IC delays calculated for the launch and the latch clock? Is the STA using different operating conditions or delays? - for example max for launch and min fo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

No go - I get error - the ALTCLKCTL does not accept the XAUI interface rx_clk as a source

Error: inclk[0] port of Clock Select Block "ALTCLKCTRa:ALTCLKCTRa|ALTCLKCTRa_altclkctrl_lef:ALTCLKCTRa_altclkctrl_lef_component|sd2" is driven by an illegal source, but must be driven by a clock pin or a PLL's CLK or FBOUT output File: /home/llocascio/ETH10G_PP/ALTCLKCTRa.v Line: 67

Info: Input port INCLK[0] of node "ALTCLKCTRa:ALTCLKCTRa|ALTCLKCTRa_altclkctrl_lef:ALTCLKCTRa_altclkctrl_lef_component|sd2" is driven by XAUI_PHY:XAUI_PHY|altera_xcvr_xaui:xaui_phy_inst

WHat is the FBOUT option?