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Altera_Forum
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14 years ago

STA Timimg Report Question

Why does the same clock path have different IC delays calculated for the launch and the latch clock? Is the STA using different operating conditions or delays? - for example max for launch and min fo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Is there something in your design that would make it do that? It should be going through two global buffers without a reason. That being said, I think I saw it once and filed it with Altera. I think the way I got around it was assigning the signal to a Global clock in the Assignment Editor. It already was doing that, but tricked it not to do it again. Don't ask me why...