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Altera_Forum
Honored Contributor
Honored ContributorSTA Timimg Report Question
Why does the same clock path have different IC delays calculated for the launch and the latch clock? Is the STA using different operating conditions or delays? - for example max for launch and min fo...
Altera_ForumHonored Contributor
Honored ContributorThe clock is gated and also has clock mux to select between two clocks so maybe that causes the buffer insertion. But why in only the launch path?
Since I am new to FPGAs how do I know if it is a Global clock and how to assign it if it isnt? Should I create a generated clock on the output of the mux and assign it to a Global clock?
