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Altera_Forum
Honored Contributor
Honored ContributorSTA Timimg Report Question
Why does the same clock path have different IC delays calculated for the launch and the latch clock? Is the STA using different operating conditions or delays? - for example max for launch and min fo...
Altera_ForumHonored Contributor
Honored ContributorGated clocks are the bane of FPGA design. Unlike an ASIC(if that's your background), the fitter can't add/remove delays to the clock tree to balance them out. What you're doing is a good solution. Converting to clock enables when possible is another solution. In general, try to avoid them, and if you can't try to minimize interfaces between gated and non-gated domains.
