Setup/Hold time margin calculation for FPGA

It looks like altera doesn't state the setup/hold time of its FPGA io.

Instead, you enter setup/hold time for inputs and the tool automatically inserts delays to achieve them. Alternatively, you can enter delays but then you will need to know the internal flip setup/hold values.

The formulas for setup/hold time for any case of source synchronous interface is same(data and clk coming in together). Referred to the pins the equations are:

setup = reg setup + data delay - clk delay

hold = reg hold -data delay + clk delay

remember to add board delays if you know...

Thanks KAZ,

I could understand that, I can use the same formula as like doing with other ICs.

But my problem is, I have to get the timing parameter (setup/hold time) from FPGA end. But in their datasheet, they gave it for IOE and LE_FF. I can't get how to use this values for my margin calculation.

In stead of doing with tool, I tried to calculate by formulas.

My question is, How to derive the FPGA signal's setup/hold time from the timing parameters (Tsu/Th/Tco for IOE and LE_FF) as given in their datasheet ?

http://www.altera.com/literature/hb/cyc2/cyc2_cii51005.pdf

Pg - 19

Regards,

-V

Hi,

the reg setup or reg hold in above equations mean those values of registers that you use to capture input. Using them in equations is not practical as you need to know the delays(default or yours) between pins and registers then enter above equations to get setup/hold at pins.

I rather decide setup/hold in quartus for my pins and let it work out the delays. The best values of setup/hold depend on your incoming data relation to its clk (e.g. Tco of external chip or board delay effects). It is common to set hold time to zero as this helps safer design.

edit:remember to set your input registers as fast io otherwise the slower LE registers will be used.

Why wouldn't you use the Quartus timing engine(TAN or TimeQuest) to get these numbers? The bottom line is that there are too many parameters to put them into a datasheet. A few things they depend on:

- The clock, whether it uses a PLL, how that PLL is configured, what type of global resource it uses, etc.

- I/O standards

- Package layout(even if the silicon were identical, different I/O are bonded out in different manners)

- Loading(along local routes, at the I/O, etc.)

I'm guessing you want a generic number and don't care if it's a little pessimistic, but if you start with the Quartus values and round up a little, that might be what you're looking for.

Thanks KAZ/Rysc,

I will try the values with the Altera tool :)

Let me explain my view of input setup/hold optimisation with an example:

If your external chip register(that sources data and clk to fpga) has a Tco of 2ns then and assuming board delay is practically equal for all data bits and clk then this Tco of 2 nsec holds on as signals arrive at fpga pins.

assume your input data clk = 100MHz(period = 10 ns)

Thus at fpga pins the data will transition 2ns after clk edge and is stable from this point on for 10 ns. In other words at pins: there is 8ns safe window before the clk edge and only 2ns after clk edge. As both data and clk travel through FPGA TH is liable to violation due to this narrow margin.

You can set quartus for an input Tsu to 8 ns and TH to 2 ns but to be on safer side:

Ask quartus to delay data more relative to clk by setting TH to zero. Quartus will then insert more delay e.g. 3ns pushing the data transition some 5 ns as it arrives at flip. The remainder of clk period of 5ns should give safe margin for Tsu.

Interestingly some recent DACs from Analog Devices have automated this timing optimisation at their input data by special circuitry comparing clk edge to data edge then shifting clk phase.