Setup/Hold time margin calculation for FPGA

Hi,

the reg setup or reg hold in above equations mean those values of registers that you use to capture input. Using them in equations is not practical as you need to know the delays(default or yours) between pins and registers then enter above equations to get setup/hold at pins.

I rather decide setup/hold in quartus for my pins and let it work out the delays. The best values of setup/hold depend on your incoming data relation to its clk (e.g. Tco of external chip or board delay effects). It is common to set hold time to zero as this helps safer design.

edit:remember to set your input registers as fast io otherwise the slower LE registers will be used.