Setup/Hold time margin calculation for FPGA

Why wouldn't you use the Quartus timing engine(TAN or TimeQuest) to get these numbers? The bottom line is that there are too many parameters to put them into a datasheet. A few things they depend on:

- The clock, whether it uses a PLL, how that PLL is configured, what type of global resource it uses, etc.

- I/O standards

- Package layout(even if the silicon were identical, different I/O are bonded out in different manners)

- Loading(along local routes, at the I/O, etc.)

I'm guessing you want a generic number and don't care if it's a little pessimistic, but if you start with the Quartus values and round up a little, that might be what you're looking for.