Setup/Hold time margin calculation for FPGA

Let me explain my view of input setup/hold optimisation with an example:

If your external chip register(that sources data and clk to fpga) has a Tco of 2ns then and assuming board delay is practically equal for all data bits and clk then this Tco of 2 nsec holds on as signals arrive at fpga pins.

assume your input data clk = 100MHz(period = 10 ns)

Thus at fpga pins the data will transition 2ns after clk edge and is stable from this point on for 10 ns. In other words at pins: there is 8ns safe window before the clk edge and only 2ns after clk edge. As both data and clk travel through FPGA TH is liable to violation due to this narrow margin.

You can set quartus for an input Tsu to 8 ns and TH to 2 ns but to be on safer side:

Ask quartus to delay data more relative to clk by setting TH to zero. Quartus will then insert more delay e.g. 3ns pushing the data transition some 5 ns as it arrives at flip. The remainder of clk period of 5ns should give safe margin for Tsu.

Interestingly some recent DACs from Analog Devices have automated this timing optimisation at their input data by special circuitry comparing clk edge to data edge then shifting clk phase.