Setup/Hold time margin calculation for FPGA

It looks like altera doesn't state the setup/hold time of its FPGA io.

Instead, you enter setup/hold time for inputs and the tool automatically inserts delays to achieve them. Alternatively, you can enter delays but then you will need to know the internal flip setup/hold values.

The formulas for setup/hold time for any case of source synchronous interface is same(data and clk coming in together). Referred to the pins the equations are:

setup = reg setup + data delay - clk delay

hold = reg hold -data delay + clk delay

remember to add board delays if you know...