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Altera_Forum
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16 years ago

Setup/Hold time margin calculation for FPGA

Hi, In my design, I used cyclone II FPGA. I just want to calculate the setup/hold time margin for some interfaces (like PCI 32/66). For this calculation, I need the setup/hold time of the signa...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Thanks KAZ,

I could understand that, I can use the same formula as like doing with other ICs.

But my problem is, I have to get the timing parameter (setup/hold time) from FPGA end. But in their datasheet, they gave it for IOE and LE_FF. I can't get how to use this values for my margin calculation.

In stead of doing with tool, I tried to calculate by formulas.

My question is, How to derive the FPGA signal's setup/hold time from the timing parameters (Tsu/Th/Tco for IOE and LE_FF) as given in their datasheet ?

http://www.altera.com/literature/hb/cyc2/cyc2_cii51005.pdf

Pg - 19

Regards,

-V