sensitivity list. VHDL

The sensitivity list is used only during simulations in VHDL

VHDL was written a long time ago and for simulation. I'm guessing simulators back then just looked at the sensitivity list, and weren't able to infer what should be in there. I think VHDL now lets you put a * or something like that to imply "whatever you need in here". I forget the exact syntax. (Technically, it might help readability too, since you have a location to determine what all the sources are, but I doubt it's overly useful for that.)

I am not completely with you about the role of the sensitivity list. For me, it is not only a tool for the simulator, it can also impact the synthesis.

process(a, b)
begin
    if a = '1' and b = '0' then
        c <= '1'
    else
        c <= '0'
    end if;
end process;

process(a)
 begin
    if a = '1' and b = '0' then
        c <= '1'
    else
        c <= '0'
    end if;
end process;

This may be true, but the fact is when you actually synthesise it it doesnt produce a latch. It warns you that b should be in the list and then just generates the logic as the first example.

But that means that the synthesis tool does not follow the rule of VHDL. It is quite strange, no ?

Different synthesis tools may behave differently in this respect - i.e. one may produce a latch, another may not. It is exceptionally bad practice to ignore the sensitivity list on the assumption that the synthesis tool "will sort it out". The sensitivity list is there for a reason.