Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorsensitivity list. VHDL
Hello, Maybe this is an elementary question, :D. Why I need to add all the signals that I use in a process to the sensitivity list. If I add them or not, I am getting the same results...
Altera_ForumHonored Contributor
Honored ContributorBut that means that the synthesis tool does not follow the rule of VHDL. It is quite strange, no ?
