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Altera_Forum's avatar
Altera_Forum
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16 years ago

sensitivity list. VHDL

Hello, Maybe this is an elementary question, :D. Why I need to add all the signals that I use in a process to the sensitivity list. If I add them or not, I am getting the same results...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

This may be true, but the fact is when you actually synthesise it it doesnt produce a latch. It warns you that b should be in the list and then just generates the logic as the first example.