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VHDL was written a long time ago and for simulation. I'm guessing simulators back then just looked at the sensitivity list, and weren't able to infer what should be in there. I think VHDL now lets you put a * or something like that to imply "whatever you need in here". I forget the exact syntax. (Technically, it might help readability too, since you have a location to determine what all the sources are, but I doubt it's overly useful for that.)
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This is all correct. Missing signals in a sensitivity list will give a warning in synthesis, and will give incorrect results in simulation.
Sensitivity lists are useful as they can help speed up simulation by ignoring events on anything thats not important. But the VHDL 2008 standard now lets you do this:
process(all)
to let you be sensitive to all signals declared in the entity. Not sure if quartus will compile this yet though, but it should work fine in newer versions of modelsim.
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