sensitivity list. VHDL

VHDL was written a long time ago and for simulation. I'm guessing simulators back then just looked at the sensitivity list, and weren't able to infer what should be in there. I think VHDL now lets you put a * or something like that to imply "whatever you need in here". I forget the exact syntax. (Technically, it might help readability too, since you have a location to determine what all the sources are, but I doubt it's overly useful for that.)