sensitivity list. VHDL

I am not completely with you about the role of the sensitivity list. For me, it is not only a tool for the simulator, it can also impact the synthesis.

For example, take the following codes. The first process has a sensitivity list with all the signals that are read during the process, and this lead to a combinatorial circuit.

The second process misses the b input in its sensitivity list. This implies that if a stays at the same level and b changes, the process is not activated and the output is not modified, so this leads to a latch in the circuit, so the process is no more pure combinatorial.

process(a, b)
begin
    if a = '1' and b = '0' then
        c <= '1'
    else
        c <= '0'
    end if;
end process;

process(a)
 begin
    if a = '1' and b = '0' then
        c <= '1'
    else
        c <= '0'
    end if;
end process;