Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorsensitivity list. VHDL
Hello, Maybe this is an elementary question, :D. Why I need to add all the signals that I use in a process to the sensitivity list. If I add them or not, I am getting the same results...
Altera_ForumHonored Contributor
Honored ContributorDifferent synthesis tools may behave differently in this respect - i.e. one may produce a latch, another may not. It is exceptionally bad practice to ignore the sensitivity list on the assumption that the synthesis tool "will sort it out". The sensitivity list is there for a reason.
I think it was VHDL 2008 (aka VHDL 2006 as that was when it was drafted) that introduced the "all" in the sensitivity list - whilst Modelsim (uurrrggghh) may support this, be careful because your synthesis tool may not - Xilinx 11.1 definitely does not.
