PLL outputs to drive 50 ohm loads

The maximum ratings say -25/+40 mA, also internal series termination isn't supported for the 3.3 V node. It mainly depends on the required receive level which isn't nebtioned in your post.

If you are driving a single load from each output consider using serial termination as it avoids the constant DC load of the parallel termination at the far side. In Cyclone III (and most other devices) series termination is easy.

Thanks. I did consider using series termination. However, it is not as good as parallel termination. If Cyclone III series termination is used, 2 extra I/Os, rup and rdn will be used or 2 external resistors will be used.

Thanks.

You can (almost) always use serial termination for single-ended point to point connections. I overlooked FvM's observation that unfortunately you can not apply series terminations for 3.3V outputs. I suggest you add a series resistor externally. The trick here is to estimate what the series resistance of the driver inside the FPGA is, I usually specify a 39 ohm external resistor for a 50 ohm Z0. A 0402 resistor can fit directly to the BGA escape via. Also the transmission line you route on the PCB doesn't have to be a 50 ohm either, you could opt to route for 60 ohm (or even more).

For best DAC (or ADC) performance, you shouldn't use a clock from a FPGA PLL. The clock jitter introduces a considerable phase noise amount. This is particularly the case in communication (or similar measurement) applications, where a high frequency signal is generated by the DAC. A LVDS output high frequency crystal oscillator will give better performance for this application.

I understand what you were saying. In my case, I have to use a PLL clock output to drive the DAC clock input. This is because the DAC clock and DAC digital data lines from the FPGA are not independent. The DAC clock has to be synchronized with the other clock.

I mainly stumbled upon best performance. You can expect good performance with FPGA PLL clock, I'm using it in many projects. But if you check the PLL jitter specification, it really isn't outstanding. As an additional problem, using single ended IO standard, you also add FPGA originated switching noise and respective jitter to the clock output. A differential standard would be better, the same applies to the FPGA master clock input.

Correct me if I'm wrong but it appears based on the current calculation that bcao is using a 1.5V single-ended standard correct?