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Altera_Forum
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16 years ago

PLL outputs to drive 50 ohm loads

I need two outputs from a single PLL of CYCLONE-III 3C16. Both the outputs are single-ended. One of outputs is 100MHz and the other is 120MHz-200MHz which will be dynamically configured through NIOS-...
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Altera_Forum
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16 years ago

For best DAC (or ADC) performance, you shouldn't use a clock from a FPGA PLL. The clock jitter introduces a considerable phase noise amount. This is particularly the case in communication (or similar measurement) applications, where a high frequency signal is generated by the DAC. A LVDS output high frequency crystal oscillator will give better performance for this application.