PLL outputs to drive 50 ohm loads

Thanks.

One of clocks goes to a high-speed DAC in single-ended mode. In the single-ended mode, it needs 50ohm parallel termination for its best performance. The DAC could accept LVDS. The issue with LVDS from Cyclone-III FPGA is that a bank has to be configured as LVDS. As a result, we don't have enough I/O pins.

The other clock (120MHz-200MHz) goes to the single-ended clock input of a device. Ideally, it is in 50ohm parallel termination.

I can find up-to 166MHz clock drivers which are able to drive single-ended 50 ohm impedance with 2 inputs being synchronized.