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Honored Contributor
Honored ContributorPLL outputs to drive 50 ohm loads
I need two outputs from a single PLL of CYCLONE-III 3C16. Both the outputs are single-ended. One of outputs is 100MHz and the other is 120MHz-200MHz which will be dynamically configured through NIOS-...
Altera_ForumHonored Contributor
Honored ContributorI understand what you were saying. In my case, I have to use a PLL clock output to drive the DAC clock input. This is because the DAC clock and DAC digital data lines from the FPGA are not independent. The DAC clock has to be synchronized with the other clock.
