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Altera_Forum
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16 years ago

PLL outputs to drive 50 ohm loads

I need two outputs from a single PLL of CYCLONE-III 3C16. Both the outputs are single-ended. One of outputs is 100MHz and the other is 120MHz-200MHz which will be dynamically configured through NIOS-...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I understand what you were saying. In my case, I have to use a PLL clock output to drive the DAC clock input. This is because the DAC clock and DAC digital data lines from the FPGA are not independent. The DAC clock has to be synchronized with the other clock.