PLL outputs to drive 50 ohm loads

I mainly stumbled upon best performance. You can expect good performance with FPGA PLL clock, I'm using it in many projects. But if you check the PLL jitter specification, it really isn't outstanding. As an additional problem, using single ended IO standard, you also add FPGA originated switching noise and respective jitter to the clock output. A differential standard would be better, the same applies to the FPGA master clock input.