PLL outputs to drive 50 ohm loads

FvM and jakobjones, thank you very much. The receivers in my application do NOT accept Vref and this is one of reasons SSTL Class I or HSTL Class I was not considered. At 3.3V level, as FvM said, FPGA is not able to source or sink enough current to a 50 ohm parallel termination. I am going to use 2 separate clock drivers to drive 2 50-ohm loads although there will be some differences of jitters and delays. The solution is to use a configurable PLL and dynamically adjust phase shift through NIOS-II.