Need help with timing constraints/closure for an EMIF design

Any update on this?

Regards,

Richard Tan

Hi Richard,

Apologies for the delay in responding.

I will check with the team if we can share the design. I haven't still tried to change the reset to synchronous in the RTL. I will try doing that today or tomorrow and will update here what happens.

Best,

BB

Any update on this?

Do you need further help in regards to this case?

Regards,

Richard Tan

I will need your design (Project > Archive Project) to investigate why the asynchronous clear to synchronous clear conversion is not taking place. The report alone does not provide enough information to determine the cause.

Alternatively, you can remove the asynchronous clear/reset by changing your code

example, use:

always @(posedge clk)

instead of

always @(posedge clk or negedge rst_n)

You may check AN917, 1.4.1. Reset Coding Techniques, for further details.

https://www.intel.com/content/www/us/en/docs/programmable/683539/20-4/an-917-reset-design-techniques-for-architecture.html

Regards,

Richard Tan

Your report show a very high logic level with a 10-12 of levels of logic. This is not recommended as this will increase the delay on a timing path.

You will need to reduce the logic level to around 3 -5 by adding pipeline register. The number of logic level depends on your design requirement, you might need to reduce further to close timing.
Take note that adding pipeline will increase the clock latency.

https://www.intel.com/content/www/us/en/docs/programmable/683664/19-3/reduce-logic-levels.html

Regards,

Richard Tan

It would be helpful to show a timing report from the timing analyzer to see what paths are actually failing timing.

Hi sstrell,

Thanks for your response. I probably didn't gave a good description of the issue. EMIFs are not really an issue in this case. The design was closing timing and working all right until we enabled/added some design and from closing timing, the timing failure shot to around 3.8 ns. This has been bought down to 2ii with design changes. This failure caused errors in the design so I started looking in to recommendations from fit.forward report.

As I mentioned earlier, I have forwarded the register addition suggestions to the designers. Regarding the change from asynchronous clear to synchronous clear, I enforced it in Quartus but it does not seem to take effect as the similar suggestions still persist in the fit.forward report. Hence uploaded the fit.forward reports and reached out for help. Please help with this large timigng. Let me know what other information I can provide.

Best,

BB

When trying to close timing on an EMIF, following the Fast Forward recommendations for Hyperflex is not where you should start.

Verify the options you've specified in the EMIF IP Parameter Editor and run the EMIF-specific timing reports in the Timing Analyzer. What speed are you trying to run the EMIF at?

See the user guide here: https://www.intel.com/content/www/us/en/docs/programmable/683741/24-1-19-2-8/emif-ip-timing-closure.html