Forum Discussion
BKB
Occasional Contributor
Occasional ContributorNeed help with timing constraints/closure for an EMIF design
Hi, We have a design with 2 EMIFs with user clock at 200Mhz and it had more than 3.5 ns timing failure when the RS8 logic was added. With design changes and iterations the design still fails by 2ns....
sstrell
Super Contributor
Super ContributorWhen trying to close timing on an EMIF, following the Fast Forward recommendations for Hyperflex is not where you should start.
Verify the options you've specified in the EMIF IP Parameter Editor and run the EMIF-specific timing reports in the Timing Analyzer. What speed are you trying to run the EMIF at?
See the user guide here: https://www.intel.com/content/www/us/en/docs/programmable/683741/24-1-19-2-8/emif-ip-timing-closure.html
