Need help with timing constraints/closure for an EMIF design

I will need your design (Project > Archive Project) to investigate why the asynchronous clear to synchronous clear conversion is not taking place. The report alone does not provide enough information to determine the cause.

Alternatively, you can remove the asynchronous clear/reset by changing your code

example, use:

always @(posedge clk)

instead of

always @(posedge clk or negedge rst_n)

You may check AN917, 1.4.1. Reset Coding Techniques, for further details.

https://www.intel.com/content/www/us/en/docs/programmable/683539/20-4/an-917-reset-design-techniques-for-architecture.html

Regards,

Richard Tan