Agilex7 Device Reliability Report - newer version than July 2021.
Hello, there is supposed to be a newer version out late 2022 or later. Anyone have such a report, or can confirm it does NOT exist, or know when it is supposed to release? daryl nees, Technical Solutions Specialist, Intel PSG (Altera) MAG BU
Agilex 7 M-series: Issue accessing DDR5 COMP over JTAG
Hello, I built the EMIF DDR5 COMP example design targeting the Agilex™ 7 FPGA M-Series Development Kit - HBM2e Edition (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html). I am using Quartus Pro 24.3. DDR5 appears to be working properly, the EMIF AXI-Lite driver is receiving successful calibration and signal tap shows the Test Engine successfully writing and reading from DDR5. In this design, I added a JTAG path to the DDR5 using a JTAG to Avalon Master bridge -> Address Span Extender (to extend the avalon address range from 32-bit to 44-bit) -> NoC initiator (I've tried reusing the same initiator as the test engine and also two separate initiators) -> EMIF. I am able to successfully read and write addresses 0x0000 - 0x7FFF using system-console over JTAG. However, whenever I try beyond that address range (0x8000 and up) I read only 0's and I've noticed that the rresp signal coming from the NoC initiator shows 0x2 (SLVERR). This only happens with the JTAG path, the test engine still appears to read/write the full DDR range. I've tried adjusting the security settings in Platform Designer, I've tried putting a AXI bridge in-between the address span extender and the NoC initiator, multiple NoC initiators, and the bit-width of these intitiators. As far as I can see, the JTAG path and the test engine path is very similar both in configuration and in signal tap. I've checked the path in Platform Designer and the NoC assignment values. The major differences being that JTAG starts as a 32-bit Avalon host while the test engine generates a 256-bit AXI4 manager. Please let me know if you need more information and I am looking forward to any guidance you may provide.
Agilex 7 FP32/FP16 TFlops performance calculation
Hello, I would like to calculate the following metrics for the Agilex 7 series: -Peak FP32/FP16 FMA TFlops -Peak FP32/FP16 TFlops -Peak FP32/FP16 TFlops / mm^2 of fabric How would I calculate these? I am also looking for the Local Memory Bandwidth, Memory Bandwidth, and die area of the part. Can someone assist me? Thank you for your time!
Reliability report
I am trying to access the reliability report, here:https://www.intel.com/content/www/us/en/secure/content-details/817705/programmable-solutions-group-psg-reliability-monitoring-report.html, but when I click download, I see the message below. Could you give me access to the reliability report, please? I am specifically interested in Cyclone 10 GX. Thanks, Gavin Oops, something went wrong! The page you requested has moved or doesn't exist. If you followed a link, it's probably broken - but don't worry, we've already reported it. In the meantime, why not take a look around?Quartus II Software 7.1 Installer needed
Hello, We have some legacy software that we need to recreate identically. Unfortunately, Intel doesn't offer the installers for these obsolete programs on the download page anymore. We need the 32 bit installer for Quartus II 7.1 and for the SP1 update. Thanks.Need help with timing constraints/closure for an EMIF design
Hi, We have a design with 2 EMIFs with user clock at 200Mhz and it had more than 3.5 ns timing failure when the RS8 logic was added. With design changes and iterations the design still fails by 2ns. The fit.fastforward report makes some suggestions to add register stages which I have passed on the designers and waiting response. The report also makes suggestions to change asynchronous clears to synchronous clears. I haven't made the changes in the code but I set it in qsf set_global_assignment -name FORCE_SYNCH_CLEAR ON But the the fit.fastforward report mentions that the asynchronous clear are not converted to synchronous. Please review the review report and help with timing closure. Best, BB
