Agilex 7 M-series: Issue accessing DDR5 COMP over JTAG

Hello,

I built the EMIF DDR5 COMP example design targeting the Agilex™ 7 FPGA M-Series Development Kit - HBM2e Edition (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html). I am using Quartus Pro 24.3. DDR5 appears to be working properly, the EMIF AXI-Lite driver is receiving successful calibration and signal tap shows the Test Engine successfully writing and reading from DDR5.

In this design, I added a JTAG path to the DDR5 using a JTAG to Avalon Master bridge -> Address Span Extender (to extend the avalon address range from 32-bit to 44-bit) -> NoC initiator (I've tried reusing the same initiator as the test engine and also two separate initiators) -> EMIF. I am able to successfully read and write addresses 0x0000 - 0x7FFF using system-console over JTAG. However, whenever I try beyond that address range (0x8000 and up) I read only 0's and I've noticed that the rresp signal coming from the NoC initiator shows 0x2 (SLVERR). This only happens with the JTAG path, the test engine still appears to read/write the full DDR range. I've tried adjusting the security settings in Platform Designer, I've tried putting a AXI bridge in-between the address span extender and the NoC initiator, multiple NoC initiators, and the bit-width of these intitiators.

As far as I can see, the JTAG path and the test engine path is very similar both in configuration and in signal tap. I've checked the path in Platform Designer and the NoC assignment values. The major differences being that JTAG starts as a 32-bit Avalon host while the test engine generates a 256-bit AXI4 manager.

Please let me know if you need more information and I am looking forward to any guidance you may provide.