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rgkim-intel's avatar
rgkim-intel
Icon for New Contributor rankNew Contributor
1 year ago

Agilex 7 M-series: Issue accessing DDR5 COMP over JTAG

Hello, I built the EMIF DDR5 COMP example design targeting the Agilex™ 7 FPGA M-Series Development Kit - HBM2e Edition (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits...
Board Debug
Fpga Devkit
Generic Io
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.