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rgkim-intel's avatar
rgkim-intel
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5 months ago

Agilex 7 M-series: Issue accessing DDR5 COMP over JTAG

Hello, I built the EMIF DDR5 COMP example design targeting the Agilex™ 7 FPGA M-Series Development Kit - HBM2e Edition (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits...
Board Debug
Fpga Devkit
Generic Io
AdzimZM_Altera's avatar
AdzimZM_Altera
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5 months ago

Hi rgkim-intel,


Have you trace the signal on SignalTap just in case the signal cannot transfer on JTAG?


It's looks like the EMIF IP is working well based on your description.

Can you provide Address Span Extender IP setting?


Regards,

Adzim


rgkim-intel's avatar
rgkim-intel
Icon for New Contributor rankNew Contributor
5 months ago

Hi Adzim,

Yes I can trace the signal. I was looking at the AXI4 subordinate on the NoC initiator and I can see the JTAG requests reach that point. For addresses 0x0000-0x7FFF it appears to read just fine, data comes back and rresp is 0x0. However, when reading address 0x8000 rresp changes to 0x2 (SLVERR). Please see address span extender IP configuration in the screenshot below. This should allow me to access 0x0000_0000 - 0x7FFF_FFFF from the JTAG.

Best,

Ryan