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rgkim-intel's avatar
rgkim-intel
Icon for New Contributor rankNew Contributor
1 year ago

Agilex 7 M-series: Issue accessing DDR5 COMP over JTAG

Hello, I built the EMIF DDR5 COMP example design targeting the Agilex™ 7 FPGA M-Series Development Kit - HBM2e Edition (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits...
Board Debug
Fpga Devkit
Generic Io
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi Ryan,


I have a few suggestions for debugging this issue.

  1. Try to change the Datapath width in ASE IP either reduce it or increase it and observe the different.
  2. Can also you capture the signal on AXI4 NoC Manager on NoC Initiator?


If possible, please share the SS of your SignalTap as well.


Regards,

Adzim