Forum Discussion
BKB
Occasional Contributor
Occasional ContributorNeed help with timing constraints/closure for an EMIF design
Hi, We have a design with 2 EMIFs with user clock at 200Mhz and it had more than 3.5 ns timing failure when the RS8 logic was added. With design changes and iterations the design still fails by 2ns....
sstrell
Super Contributor
Super ContributorIt would be helpful to show a timing report from the timing analyzer to see what paths are actually failing timing.
BKBThe timing report file is beyond 1.6gb. With maximum compression its 51 MB. Is there a way that I upload that file. Here the maximum limit is 23 mb. I tried splitting the file with 7z but I got an error here when I tried to upload it.
Best,
BB
