Occasional Contributor
Super ContributorYour report show a very high logic level with a 10-12 of levels of logic. This is not recommended as this will increase the delay on a timing path.
You will need to reduce the logic level to around 3 -5 by adding pipeline register. The number of logic level depends on your design requirement, you might need to reduce further to close timing.
Take note that adding pipeline will increase the clock latency.
https://www.intel.com/content/www/us/en/docs/programmable/683664/19-3/reduce-logic-levels.html
Regards,
Richard Tan
Occasional ContributorHi Richard
Thanks for reviewing the timing reports and making suggestions. We already went through inserting some pipeline stages and were able to lower the timing failure margin from 3.8 ns to around 2 ns. I was hoping someone might review the fit.fastforward suggestions and comment on why the quartus is not able to enforce the asynchronous clear to synchronous clear conversion. the fit.fforward report suggests that this might significantly improve the timing results.
Best,
BB
