Forum Discussion

Occasional Contributor

8 months ago

Need help with timing constraints/closure for an EMIF design

Hi, We have a design with 2 EMIFs with user clock at 200Mhz and it had more than 3.5 ns timing failure when the RS8 logic was added. With design changes and iterations the design still fails by 2ns....

ddr_.fit.fastforward.zip185 KB

ddr_u1.fit.fastforward.txt2.1 MB

ddr_u2.fit.fastforward.txt7.3 MB

Fpga Devkit

BKB

Occasional Contributor

7 months ago

Hi Richard,

Apologies for the delay in responding.

I will check with the team if we can share the design. I haven't still tried to change the reset to synchronous in the RTL. I will try doing that today or tomorrow and will update here what happens.

Best,

Forum Discussion

Need help with timing constraints/closure for an EMIF design

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