Forum Discussion

Occasional Contributor

8 months ago

Need help with timing constraints/closure for an EMIF design

Hi, We have a design with 2 EMIFs with user clock at 200Mhz and it had more than 3.5 ns timing failure when the RS8 logic was added. With design changes and iterations the design still fails by 2ns....

ddr_.fit.fastforward.zip185 KB

ddr_u1.fit.fastforward.txt2.1 MB

ddr_u2.fit.fastforward.txt7.3 MB

Fpga Devkit

sstrell

Super Contributor

8 months ago

It would be helpful to show a timing report from the timing analyzer to see what paths are actually failing timing.

BKB

Occasional Contributor

8 months ago

The timing report file is beyond 1.6gb. With maximum compression its 51 MB. Is there a way that I upload that file. Here the maximum limit is 23 mb. I tried splitting the file with 7z but I got an error here when I tried to upload it.

Best,

sstrell
Super Contributor
8 months ago
No, you should just run Report Timing in the Timing Analyzer and you can filter on just paths with negative slack. Why would this be 1.6 GB?
There's also the Report DDR task there.
- BKB
  Occasional Contributor
  8 months ago
  Reports attached
  MC1_200mhz_emif_usr_clk.zip12.7 MB

Forum Discussion

Need help with timing constraints/closure for an EMIF design

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