Need help with timing constraints/closure for an EMIF design

Hi sstrell,

Thanks for your response. I probably didn't gave a good description of the issue. EMIFs are not really an issue in this case. The design was closing timing and working all right until we enabled/added some design and from closing timing, the timing failure shot to around 3.8 ns. This has been bought down to 2ii with design changes. This failure caused errors in the design so I started looking in to recommendations from fit.forward report.

As I mentioned earlier, I have forwarded the register addition suggestions to the designers. Regarding the change from asynchronous clear to synchronous clear, I enforced it in Quartus but it does not seem to take effect as the similar suggestions still persist in the fit.forward report. Hence uploaded the fit.forward reports and reached out for help. Please help with this large timigng. Let me know what other information I can provide.

Best,

BB