New ContributorI'm a beginner, and after designing an adder, I wanted to use SignalTap to check the synthesized signals. However, I found that the signals are not as expected. It seems to be due to metastability issues, causing the originally stable values to randomly switch between 0 and 1. How can I correct this issue?main modulecarry adder and adder200PLLsignal tap(pre-syn)
Super ContributorHi,
does your design meet timing? If not (very likely it doesn't), why do you complain about unexpected results?
I'm not sure what you want to achieve, as a general rule:
- don't use clock as data
- don't use divided or phase shifted clocks, except for special purposes e.g. driving peripherals
Super ContributorI also suspect that the design may not meet the timing requirements. You can check out the document below for further information.
Best Regards,
Richard Tan
Super ContributorI have yet to receive any response from you in regards to my last reply. Do you need further help in regards to this case?
Best Regards,
Richard Tan
p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey
New Contributor"I recently discovered that there may be a 'bubble effect' issue. Originally, all the bits that haven't reached a carry should be 1, but it turns out there are a few 0s mixed in. I haven't resolved it yet."
Super ContributorCould you help to share your design .qar file (Project> Achieve Project) so that we could investigate what goes wrong?
Best Regards,
Richard Tan
New ContributorLike this?
Super ContributorThere is no SDC file in your design, so this is likely an issue with your design.
You can refer to this document on how to use SDC constraints:
You may also want to check out YouTube for resources related to timing analysis.
Link: https://www.youtube.com/watch?v=O6kf1_fSaIA
Best Regards,
Richard Tan
p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.
New ContributorI'm using Timing Analyzer, and when I click on 'constraints' and then 'create clock' to set up my clock signals, after I finish and compile, my clock signals disappear. What could be the issue?
Super ContributorYou might have written the constraints incorrectly, thus they are being ignored.
You can check the 'Report Ignored Constraints' and see if that's the case.
Best Regards,
Richard Tan
New Contributor"Report Ignored Constraints: No Ignored Constraints Found. By the way, I want to constrain the PLL clock. Should I set it individually, or should I use the 'derive PLL clocks' feature?
Super ContributorTechnically, both methods are equivalent, but some users may modify their PLLs and forget to update their .sdc files. Therefore, I strongly recommend sticking with "derive_pll_clocks".
Super ContributorSuper ContributorWe noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transition your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding. If you have any further questions or concerns, please don't hesitate to let us know. Thank you for reaching out to us!
Best Regards,
Richard Tan
p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.
