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jaylong's avatar
jaylong
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2 years ago

Metastable

I'm a beginner, and after designing an adder, I wanted to use SignalTap to check the synthesized signals. However, I found that the signals are not as expected. It seems to be due to metastability is...
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RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

There is no SDC file in your design, so this is likely an issue with your design.

You can refer to this document on how to use SDC constraints:

Link: https://www.intel.com/content/www/us/en/docs/programmable/683068/18-1/recommended-initial-sdc-constraints.html


You may also want to check out YouTube for resources related to timing analysis.

Link: https://www.youtube.com/watch?v=O6kf1_fSaIA


Best Regards,

Richard Tan

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.



  • jaylong's avatar
    jaylong
    Icon for New Contributor rankNew Contributor
    2 years ago

    I'm using Timing Analyzer, and when I click on 'constraints' and then 'create clock' to set up my clock signals, after I finish and compile, my clock signals disappear. What could be the issue?