Forum Discussion
jaylong
New Contributor
New ContributorMetastable
I'm a beginner, and after designing an adder, I wanted to use SignalTap to check the synthesized signals. However, I found that the signals are not as expected. It seems to be due to metastability is...
RichardT_altera
Super Contributor
Super ContributorTechnically, both methods are equivalent, but some users may modify their PLLs and forget to update their .sdc files. Therefore, I strongly recommend sticking with "derive_pll_clocks".
FvMSuper Contributor
Super ContributorHi,
I think besides using reasonable sdc statements, the test design should follow elementary FPGA design rules and get rid of using clock as data. Otherwise you hardly get meaningful results.
I think besides using reasonable sdc statements, the test design should follow elementary FPGA design rules and get rid of using clock as data. Otherwise you hardly get meaningful results.
