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jaylong's avatar
jaylong
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2 years ago

Metastable

I'm a beginner, and after designing an adder, I wanted to use SignalTap to check the synthesized signals. However, I found that the signals are not as expected. It seems to be due to metastability is...
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RichardT_altera's avatar
RichardT_altera
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2 years ago

Technically, both methods are equivalent, but some users may modify their PLLs and forget to update their .sdc files. Therefore, I strongly recommend sticking with "derive_pll_clocks".


FvM's avatar
FvM
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2 years ago
Hi,
I think besides using reasonable sdc statements, the test design should follow elementary FPGA design rules and get rid of using clock as data. Otherwise you hardly get meaningful results.