Max10 propagation delay and frequency error

You need to listen to Anand and check your pin assignments first. You've got something fundamentally wrong that has nothing to do with schmitt triggers or current drive. Also, is your digital scope aliasing and giving you a false reading?

Hi,

Are you trying to say, that by connecting the input to output directly still your are not getting expected output??

If yes,

Check the pin assignment and probe it, In the correct location on your board.

Regards

Anand

Exactly yes by connecting the input to the output I am not getting the expected output.

I got a slight improvement by removing the "schmitt trigger" setting from the input pin.

Today I have been busy with other things, but tomorrow I will try to set the maximum current to the output pin, at the moment it is set to 3.3V LVTTL with minimum current.

Thanks

Giovanni

Hi,

You have to probe exactly the Output of FPGA,

If you probe the signal after it passes through an active or passive component you will see the difference.

Also check the pin assignments.

Regards

Anand

I checked the assignment, but in my projects all the I/O pins have a specific function, these 4 pins perform the filter of a frequency signal and the output signal is incorrect, but analyzing it with the oscilloscope what appears is rather a distortion due to the delay on the fronts that deceives the frequency meter.

What kind of assignments you refer to? Phisical pins, specific property?

Thanks

Giovanni

Hi

4 pins because the signals to be filtered are two different, but my tests are aimed at only one channel, the other is off. Also the other MAX10 functions are off.

Thanks

Giovanni

Can't understand what are you trying to convey?

1. .There should be no difference between input and output if your input is connected to the output pin without any logic.

Share your project.

Regards

Anand

Here an extract from the project:

entity speed_input is

generic( board_code : integer :=16#C1#);

port (

--Gemini II bus signals

B_CLK : in std_logic; --Bus clock

...

Data : inout std_logic_vector(15 downto 8);--Bus data

Addr : in std_logic_vector(15 downto 0);--Address of internal registers

--Speed input board specific signals.

...

Speeding0_sig : in std_logic; --Input from speed transducer 0.

Speeding1_sig : in std_logic; --Input from speed transducer 1.

SS0_Out_Filt : out std_logic;--Filtered Speeding0_sig

SS1_Out_Filt : out std_logic;--Filtered Speeding1_sig

...

enable : in std_logic); --enable slot decoder

end entity;

....

SS0_Out_Filt <= Speeding0_sig;

SS1_Out_Filt <= Speeding1_sig;

end architecture;

In Speeding0_sig signal is the input and SS0_Out_Filt the output.

What I see is that the output signal is slightly behind the input signal, but this is normal.

What is not correct, however, is that the output frequency is a little higher than the input frequency (measured with the frequency meter).

Error on the signal fronts?

Hi,

If you have connected the input to output without any logical operations, You have to see the same signal with the same frequency.

1. How are you are comparing the signals using Oscilloscope and probing on hardware right?
2. Which pin in hardware are you checking/probing?

If you are seeing different signals.

1. You are checking at the wrong place on the hardware/PCB board.
2. The output of FPGA is passing through passive or active components.

Regards

Anand