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AragornStrider's avatar
AragornStrider
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2 months ago

Is VCCPD = 3.3V and VCCIO = 2.5V allowed on an Arria V?

Hi, 

I am currently using an Arria V 5AGXMA1D4F27 device. I would like to use 3.3V on VCCPD and 2.5V on VCCIO for the IO bank. The intent is to have JTAG programming done at 3.3V(the processor doing the programming has 3.3V GPIOs). All pins on the bank will be using 2.5V for normal operation in addition to having true LVDS pins on the same bank after configuration.

I could not find any documentation for this. It would be of great help to have a confirmation on if this is valid? 

Thank you for your time.

Power

4 Replies

  • AragornStrider's avatar
    AragornStrider
    Icon for New Contributor rankNew Contributor
    1 month ago

    Hi Aqid and Frank,

    Apologies for my late reply.

    Thank you so much for your valuable replies. Sorry,  I was away on vacation and missed the emails. I have taken your suggestions into consideration and gone over it with my fellow designers. The fact that we would be pushing against the limit of the pin and risk damaging the device, I chose to opt for level translators and solve my problem. It was much easier than risking the damage to the pin in case of overshoot. 

     

    Thank you both for your time, 

    Kish

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 months ago

    Hi,

    according to datasheet Vih,max of 2.5 V bank is 3.6 V. Thus it should work well with 3.3 V logic. Measures against overshoot, e.g source side driver series termination resistors should be taken however.

    Regards Frank

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 months ago

    Hi,


    Short answer: No, VCCPD = 3.3 V with VCCIO = 2.5 V is not a supported combination for Arria V.


    You need to ensure the compatibility between the VCCPD and VCCIO for an I/O bank. Refer here:

    https://docs.altera.com/r/docs/683213/current/arria-v-device-handbook-volume-1-device-interfaces-and-integration/guideline-ensure-compatible-vccio-and-vccpd-voltage-in-the-same-bank


    Below link is the supported VCCPD / VCCIO combinations for LVDS:

    https://docs.altera.com/r/docs/683213/current/arria-v-device-handbook-volume-1-device-interfaces-and-integration/i/o-standards-voltage-levels-in-arria-v-devices

     

    Notice that VCCPD = 3.3 V is not listed as a supported combination at all for banks with LVDS. The only supported VCCPD value for a 2.5 V VCCIO bank (with LVDS) is 2.5 V.

    This is also consistent with the other I/O standards.


    In another document, from the footnote 119, you can see the compatible combination VCCPD and VCCIO.

    Recommended operating conditions for VCCPD


    What you should do instead

     

    Set VCCPD = 2.5 V for your 2.5 V VCCIO bank. This is the correct and documented combination for an I/O bank running 2.5 V LVCMOS and true LVDS.

     

    For your JTAG interface at 3.3 V: the JTAG pins (TDI, TDO, TMS, TCK) on Arria V are powered by VCCPD of the bank in which the pin resides. You may need to isolate this bank specifically only for configuration purposes.


    Regards,

    Aqid