New Contributor
New ContributorHere an extract from the project:
entity speed_input is
generic( board_code : integer :=16#C1#);
port (
--Gemini II bus signals
B_CLK : in std_logic; --Bus clock
...
Data : inout std_logic_vector(15 downto 8);--Bus data
Addr : in std_logic_vector(15 downto 0);--Address of internal registers
--Speed input board specific signals.
...
Speeding0_sig : in std_logic; --Input from speed transducer 0.
Speeding1_sig : in std_logic; --Input from speed transducer 1.
SS0_Out_Filt : out std_logic;--Filtered Speeding0_sig
SS1_Out_Filt : out std_logic;--Filtered Speeding1_sig
...
enable : in std_logic); --enable slot decoder
end entity;
....
SS0_Out_Filt <= Speeding0_sig;
SS1_Out_Filt <= Speeding1_sig;
end architecture;
In Speeding0_sig signal is the input and SS0_Out_Filt the output.
What I see is that the output signal is slightly behind the input signal, but this is normal.
What is not correct, however, is that the output frequency is a little higher than the input frequency (measured with the frequency meter).
Error on the signal fronts?
