Forum Discussion
Occasional ContributorInput signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5
Hi,
I am trying to interface the FTDI601 USB Bridge (https://ftdichip.com/products/ft601q-b/) to the Stratix 10 1SG10MHN3F74C2LG_U1/U2 FPGA on our design board. The reference clock for the interface is comes from the FTDI chip along with data/command signals. The signal RXF_N that indicates data coming from the FTDI chip appears one cycle wider when looked through signaltap on Stratix 10. The signal is asserted (active low) a cycle before the valid data.
To verify that the software driving the FTDI chip and interface to FPGA is correct, We tested the example designs based on Cyclone V (https://ftdichip.com/wp-content/uploads/2024/08/cyclonev_mst_fifo32_1.2.zip) provided by FTDI (https://ftdichip.com/wp-content/uploads/2020/07/AN_421_FIFO_Bus_Master_For-FT60x.pdf).
The design waveform as seen on signaltap is correct and the terminal data reading for the loopback design but for Stratix 10 has the RXF_N signal is wider (asserted one cycle earlier than data)
For the working cyclone design the FTDI chip and the Cyclone V FPGA are on the same evaluation board (https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=830) and have a direct connection on board.
For our design we have the FTDI board (https://ftdichip.com/products/umft601a-b/) with HSMC adapter connected to the Stratix 10 FPGA through an adapter board and connector on the FPGA. The image of the adapter is attached.
I have attached signaltap image for both cyclone and Stratix.
Please help figure what could cause the widening of RXF_N on Stratix device. The same loopback design and software is used on the same FTDI chip.
18 Replies
AqidAyman_AlteraRegular Contributor
Hi Bharat,
Do you have any updates on the clock edge? Have you check it as suggested?
Regards,
Aqid
BKBHi Frank,
Thanks for looking into this. I will reconfirm the clock edge. I did notice about the delay constraints not working as intended in Stratix. The chip is capable of 100MHz but I am using it at 66 MHz.
Best,
Bharat
FvMSuper Contributor
Hi,
looking at FT601 bus timing requirements in datasheet, I believe the problem could be caused by setting FPGA generated signals (in this case OE_N, RD_N) on the wrong clock edge. The problem doesn't appear with slow Cyclone V which produces sufficient output delay to still fulfill FT601 input signal hold requirement of 4.8 ns. Faster Stratix 10 apparently doesn't. Output delay constraints seem not to work as intended.
100 MHz clocked Signaltap isn't able to visualize the problem. A sufficient fast oscilloscope or LA can.
Regards
Frank
Farabi_AlteraDiagram from FTDI user guide:
- Farabi_Altera
Hello,
When W_OOB is asserted to high, the FIFO master reads from the FIFO and discards data as long as RXF_N is asserted. RXF_N may assert multiple times while W_OOB is asserted. In streaming mode, the master read and master write data count sequence is reset depending on the corresponding OOB signal assertion.
From the diagram, the RXF_N is not controlled by Cyclone V FPGA. RXF_N may get asserted multiple times while W_OOB is asserted. So you control the W_OOB signal.
regards,
Farabi
- AqidAyman_Altera
Hello,
May I know if you have any updates on clarification needed?
- BKB
Hi,
The issue still persists. There is no failure symptom or mechanism other than RXF_n signal from FTDI chip through the board is widened by a cycle.
Best,
Bharat
- Farabi_Altera
Hello,
Just checking with your observation on the extra cycle wider , do you observe any failure symptom? If yes, can you explain what is the failure?
regards,
Farabi
