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Honored Contributor
Honored Contributorinfer true dual port asynchronous ram
hallo everyone,
i need a true dual port asynchronous ram for my selfmade soft-core project. to be hardware independent i try to infer the ram-block from vhdl-code. this is my code:--
-- Dual-Port Block RAM with Two Write Ports
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity TDPR is
generic( width : natural := 16;
depth : natural := 6);
port ( clka : in std_logic;
clkb : in std_logic;
ena : in std_logic;
enb : in std_logic;
wea : in std_logic;
web : in std_logic;
rsta : in std_logic;
rstb : in std_logic;
addra : in std_logic_vector(depth-1 downto 0);
addrb : in std_logic_vector(depth-1 downto 0);
dia : in std_logic_vector(width-1 downto 0);
dib : in std_logic_vector(width-1 downto 0);
doa : out std_logic_vector(width-1 downto 0);
dob : out std_logic_vector(width-1 downto 0));
end TDPR;
architecture syn of TDPR is
type ram_type is array ((2**depth)-1 downto 0) of std_logic_vector(width-1 downto 0);
shared variable RAM : ram_type;
begin
process(CLKA)
begin
if CLKA'event and CLKA = '1' then
if ENA = '1' then
if WEA = '1' then
RAM(conv_integer(ADDRA)) := DIA;
end if;
if rsta = '1' then -- optional reset
doa <= (others => '0');
else
doa <= ram(conv_integer(addra)) ;
end if;
end if;
end if;
end process;
process (CLKB)
begin
if CLKB'event and CLKB = '1' then
if ENB = '1' then
if WEB = '1' then
RAM(conv_integer(ADDRB)) := DIB;
end if;
if rstb = '1' then -- optional reset
dob <= (others => '0');
else
dob <= ram(conv_integer(addrb)) ;
end if;
end if;
end if;
end process;
end syn;
